The present invention relates to integrated circuit design tools, and more particularly, to a system for placing dummy tiles in the metal layers of an integrated circuit design.
The semiconductor industry has witnessed a rapid and consistent miniaturization of electronic devices with the introduction of deep submicron (DSM, L≦0.35 microns) and ultra-deep submicron (UDSM, L≦0.1 microns) technologies. Reduction of device sizes has led to an increase in device density with thousands of complementary metal-oxide semiconductor (CMOS) transistors being integrated on a single die. Miniaturization has also introduced several design challenges, especially for semiconductor devices that include multi-layered interconnect lines. The density of interconnect lines varies across different layers of a design. Such a varying pattern often leads to breaking of interconnect lines during fabrication, such as during chemical-mechanical polishing (CMP), which reduces manufacturing yield. It is possible to address some of these process-related issues during the circuit design stage of the semiconductor device.
A known technique to unify the pattern density of the interconnect lines is by placing dummy tiles in proximity to the interconnect lines that do not meet certain predefined density requirements (known as tiling process). The tiling process is carried out during the design stage using commercially available electronic design automation (EDA) tools such as GTsmooth provided by Xyalis, Inc. of Grenoble, France.
FIG. 1 shows a schematic layout diagram of a metal layer of a conventional integrated circuit design 102. The integrated circuit design 102 includes a plurality of interconnect lines 104. An EDA tool identifies those areas of the design 102 where the interconnect pattern density does not meet predefined density requirements and inserts dummy tiles 106 in those areas. Inserting dummy tiles 106 makes the pattern density more uniform, which improves the efficiency of the CMP process and leads to higher manufacturing yield.
Though the predefined density requirements help in achieving a uniform pattern density, they introduce a new set of design challenges. Inserting dummy tiles increases coupling or parasitic capacitance between the interconnect lines, which degrades signal integrity and increases signal transmission delay. The impact of parasitic capacitance is compounded if the interconnect lines are at different voltage levels. Tiling algorithms used by existing EDA tools do not account for the impact of voltage difference during the tiling process. Moreover, today's semiconductor devices often include multiple power domains. Interconnect lines that connect different voltage domains often have a long parallel run length and experience different noise effects, which have to be addressed during the design stage. For example, routing patterns along input/output (I/O) pads of a semiconductor device involves long parallel lengths of interconnect lines that operate at both core and pad voltage levels, and the addition of dummy tiles between such interconnect lines adversely impacts the noise effects, which further leads to design complexities in characterizing the noise.
Therefore, it would be advantageous to have a system and method for placing dummy tiles in an integrated circuit design that reduces the impact of parasitic capacitance on interconnect lines operating at different voltage levels, reduces signal transmission delays and enhances signal integrity of the integrated circuit design, and overcomes the above-mentioned limitations of existing systems for placing dummy tiles in an integrated circuit design.